Cadence Design Systems Sigrity 2019 HF001

The Allegro Sigrity development team has released an HF001 to Sigrity 2019. The product family Allegro Sigrity consists of signal and power integrity simulation tools printed circuits and IC-Packages.

The following new features have been added to the release:
Celsius Thermal Solver Enhancements
The top release highlights of Celsius Thermal Solver are provided below.
Expanded Electrical-thermal Analysis Capability to Heterogeneous Packaging and 3D-IC Designs.
After integration with Voltus (Chip Power Sign-off tool), the Celsius electrical-thermal analysis capability has now been extended to allow integrated 3D-IC, TSV, and PKG designs.
Enhanced Transient Thermal Analysis of IC Designs Including Multiple Power Modes within the Chip
The transient thermal analysis capability of Celsius has been enhanced to allow multiple power modes within the chip.
Implemented Extensive JEDEC Standard Environments for Thermal Characterization of Packages with PCBs
Celsius allows the use of JEDEC standard specifications as templates for test-board design and analysis. This ensures standardized thermal analysis and measurements for consistency.
Implemented Component Thermal Models for Electronic Packages
Using Celsius, you can now create generic component thermal models that are commonly used in the electronic packaging industry. Celsius supports the following thermal models: Two Resistor Model, Delphi Model, and the Voltus Thermal Model.
Clarity 3D Solver Enhancements
The top release highlights of Clarity 3D Solver are provided below.
Native Windows Support Added
The Clarity 3D solver has been enhanced such that now you no longer require a Hyper-V machine to run Clarity simulations on a standalone Windows machine.
Dielectric Material Support Added
Two new options, Isotropic and Anisotropic, have been added in the Dielectric tab of the Material Manager form in Clarity 3D Layout and Clarity 3D Workbench that enable you to specify the dielectric materials as isotropic or anisotropic.
Support Added to Automatically Calculate the Maximum Length of a Signal Net
In this release, if you specify -1 in the Signal Net Max Edge Length field and select the Local Map option, Clarity 3D Layout and Clarity 3D Workbench automatically calculate the maximum edge length for signal nets during mesh generation.
Port Wizard Enhanced in Clarity 3D Workbench
You can now use the Port Wizard in Clarity 3D Workbench to create ports for discrete components, such as resistors, inductors, and capacitors.
Support for SPICE Models using Broadband SPICE Added in Clarity 3D Layout
A new option, Generate SPICE model by BBS, has been added in the workflow pane that enables you to automatically convert the network parameter results for the current simulation to a SPICE blackbox model.
Support Added for Cut-Stitch Flow
Support for Cut and Stitch flow has been added in Clarity 3D Layout. The Cut and Stitch flow speeds up the simulation by splitting one project into several subdesigns and solving them individually.
Gds2Spd Translator Enhanced
You can now perform GDS to SPD translation without importing a .map, .layermap, or .tech file in Gds2Spd Translator. The translator also lets you specify the design type for translation, set up layers and labels for translation, perform automatic clustering of vias, and translate dielectric layers as metal layers.
Sigrity Executables no Longer Available in SPB Installation
This is an early notification for users who use Sigrity Aurora, Allegro IDA, Topology Explorer, or SystemSI products from Allegro schematic or layout editors. Starting with the Allegro Release 17.40-2019 QIR1 release that is scheduled to be released in May 2020, you will have to install both Sigrity 2019 HF1 or a later version and OrCAD and Allegro Release 17.40-2019 QIR1 or a later version to be able to use these products. This will ease your installation experience and ensure that you access the latest Sigrity features and enhancements from Allegro schematic or layout editors.
When you will install Sigrity 2019 HF1 or a later version, the SIGRITY_EDA_DIRvariable will be set to point to the installation location. This variable will be used by the Allegro schematic and layout editors to access the correct Sigrity 2019 installation when using Sigrity Aurora, Allegro IDA, Topology Explorer, and SystemSI products.

Signal integrity (SI) is the bane of most system designers. Getting those signals to pass intact through all the twists and turns of your design can be a maddening experience. But modern signal integrity design and analysis is the enabling soul of most of today’s high-performance systems. Cadence’s Sigrity tools are an industry leader in the signal and power integrity.

Integrated with Cadence PCB and IC package design tools, the Sigrity solutions for signal integrity (SI) and power integrity (PI) provide advanced analysis both pre- and post-layout. Operating early in the design cycle allows for "what if" scenario exploration, sets more accurate design constraints, and reduces design iterations. Sigrity tools read and write directly to the Allegro PCB and IC package design database for fast and accurate integration of results. It provides a SPICE-based simulator and embedded field solvers for extraction of 2D and 3D structures. It supports transistor-level and behavioral I/O modeling, including power-aware simulation using IBIS models. Parallel bus and serial channel architecture can be explored pre-layout to compare alternatives, or post-layout for a comprehensive analysis of all associated signals.
Sigrity Tech Tips: How to Import Optimized 3D Structures Into Your Design Tool After 3D EM Analysis

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products-from chips to boards to systems-in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine’s 100 Best Companies to Work For.

Product: Cadence Design Systems Sigrity
Version: 2019 HF001
Supported Architectures: x64
Website Home Page : http://www.cadence.com

Language: english
System Requirements: PC *
Supported Operating Systems: *
Software Prerequisites: Cadence Design Systems Sigrity 2019 and above
Size: 3.4 Gb

System Requirements:
Supported Operating Systems:
Microsoft Windows 7 all versions (64-bit)
Windows 10 (64-bit)
Windows 2012 Server (All service packs)
Windows 2016 Server (All service packs).
Note: Clarity 3D Solver and Celsius with Hyper-V are not supported on Windows 7.
CPU: Intel Core i7 4.30 GHz or AMD Ryzen 7 4.30 GHz with at least 4 cores
RAM: 8 GB RAM / 64 GB RAM or higher
Space: 50 GB free disk space / 500 GB free disk space SSD is recommended for primary operating system (OS) and simulation working directory
Internet: Microsoft Internet Explorer 9.0 or later
Display: 1,024 x 768 display resolution with true color (16bit color) / Large monitor (or two) with Full HD resolution or higher
GPU: Dedicated graphics card with 1 GB video memory or higher.